Exemplary embodiments of the present invention relate to a semiconductor memory device, and more particularly, to a bitline sense amplifier.
A basic operation of a memory device is to write or store an external data, and read the written or stored data. A basic unit for storing data is called a cell. In such a memory device, one capacitor is used for storing one data. To precisely read data stored in the capacitor and precisely transfer the read data to the outside, the polarity of the data stored in the cell must be correctly determined. Therefore, a bitline sense amplifier (BLSA) for sensing and amplifying data is provided in the semiconductor memory device.
FIG. 1 is a circuit diagram of a conventional semiconductor memory device including a cell array and a bitline sense amplifier.
Referring to FIG. 1, a bitline pair BL and /BL coupled to a bitline sense amplifier 110 is precharged to a precharge voltage VBLP in a normal mode. When a word line WL1 is enabled, a cell transistor 101 coupled to the word line WL1 is turned on, and data stored in a capacitor is transferred to the bitline BL through a channel of the cell transistor 101 (charge sharing). At this time, the bitline bar /BL maintains the precharge voltage VBLP, and the potential of the bitline BL is changed through charge sharing.
The bitline sense amplifier 110 senses and amplifies a potential difference (dV) between the bitline BL and the bitline bar /BL.
Unlike an ideal bitline sense amplifier, a real bitline sense amplifier may not exactly sense and amplify a very slight potential difference (dV) between the bitline pair BL and /BL. A sensing operation is successfully performed when the potential difference (dV) between the bitline pair BL and /BL is more than a predetermined level, and this potential difference (dV) is called an offset voltage of the bitline sense amplifier 110. If the potential difference (dV) between the bitline BL and the bitline bar /BL is less than the offset voltage, the bitline sense amplifier 110 may not ensure a correct sensing operation. That is, a sensing margin is reduced. One of factors that causes the offset voltage may be a mismatch of the bitline sense amplifier 110. The bitline sense amplifier 110 includes a latch configured with two inverters. PMOS transistor pairs and NMOS transistor pairs constituting the two inverters must be equally fabricated. However, in practice, a structural layout may not be designed to be exactly symmetrical. Even though the layout is designed to be symmetrical, patterns may not be exactly formed as designed. Moreover, contacts may not be equally defined. For the above and other reasons, the mismatch of the bitline sense amplifier 110 may always exist. Therefore, there is a need for a technology that can easily determine and regulate the mismatch of the bitline sense amplifier 110.
In general, a high voltage VPP higher than a power supply voltage is used as a well bias of a PMOS transistor constituting the bitline sense amplifier 110, and a low voltage VBB lower than a ground voltage is used as a well bias of an NMOS transistor constituting the bitline sense amplifier 110. In FIG. 1, a pull-up voltage of the bitline sense amplifier 110 is supplied through a line RTO, and a pull-down voltage of the bitline sense amplifier 110 is supplied through a line SB. When a bitline isolation signal BIS is activated, the cell array and the bitline sense amplifier 110 are electrically coupled to each other. When the bitline isolation signal BIS is deactivated, the cell array and the bitline sense amplifier 110 are electrically decoupled from each other. Moreover, when a bitline equalization signal BLEQ is activated, the bitline pair BL and /BL is precharged to the precharge voltage VBLP.